Products & Services – 糖心Vlog一区二区精品, the ultra-low power embedded IP specialist

When Low Power is Paramount

Low power design has become THE critical issue for SoC developers. Many applications demand reduced power consumption in the form of both lower standby power and substantial cuts in dynamic power as the trend towards 鈥渁lways-on鈥� accelerate. Innovative Artificial Intelligence, IoT, wearables, medical, mobile, automotive and networking products all require聽蝉耻谤别颁辞谤别鈥檚聽power optimizing technologies and capabilities. 糖心Vlog一区二区精品 low power design capabilities and standard products are silicon-proven, process independent, variability tolerant and features market leading dynamic & static power consumption.

OUR PRODUCTS

CompuRAM

In-memory computing

MiniMiser

Custom register file architecture

cryomem + cryoip

Advanced cryogenic semiconductor IP

powermiser

Streamline low power SRAM IP

EverOn

Ultra low voltage SRAM IP

powermiser plus

New benchmark for ultra low voltage

糖心Vlog一区二区精品, the ultra-low power embedded IP specialist

颁辞尘辫耻搁础惭鈩�

颁辞尘辫耻搁础惭鈩� provides In Memory Computing (IMC) that will enable solutions for computing at the Edge to be more power efficient. At present, sensor data often has to be sent from an IoT device to a server for processing, which creates a connectivity requirement and an unavoidable latency. For time critical applications this is not acceptable and so there is a drive to do more computation within the device itself, i.e., AI processing at the Edge. Power is a significant design constraint in IoT devices, and so any extra AI-related computation must be done in a power-efficient way. 蝉耻谤别颁辞谤别鈥檚 existing low-power memory solutions already provide a way to add the significant extra memory needed by AI applications without dramatically increasing power requirements. In-memory computing provides further power savings by reducing the need to move large amounts of data around within a chip, as the initial processing of data is carried out very close to the memory array itself.

Our intimate knowledge of memory technology means that we have been able to create a solution for the next technology demand of integrating arithmetic operations within the memory. It is another example of us seeing what the industry will require in the near future and developing a solution that will be ready when the need for AI at the Edge becomes mainstream. Cutting power consumption is what we do as we have proven with our existing technologies, such as our 贰惫别谤翱苍鈩� and 笔辞飞别谤惭颈蝉别谤鈩� SRAM families that enable near threshold operation and 50% dynamic power cuts respectively. Our solutions are all designed to making it possible to create products for the next generations of ultra-low power applications that could not exist without their power reducing techniques.

In the same way that on-chip memory is better, faster and more power efficient than transporting data back and forth to off-chip memory, integrating memory and compute capability offers even more significant power saving benefits. 蝉耻谤别颁辞谤别鈥檚 in-memory compute technology achieves this integration by embedding arithmetic capability deep within the memory array in a way that is compatible with its existing silicon-proven, low-power memory design.

惭颈苍颈惭颈蝉别谤鈩�

惭颈苍颈惭颈蝉别谤鈩�聽is a tuneable multi-port register file architecture that can support both low power and high-performance applications. Its unique implementation reduces power consumption by over 50% and gives developers a new way of optimising the power envelope for their design. By swapping off-the-shelf register files with聽MiniMiser聽significant power savings can be realised. By reviewing the application鈥檚 operational demands designers can further enhance this by introducing multiple performance modes tied to various operating voltages thereby ensuring the SoC is tuned to application need. As聽MiniMiser聽is not based on the foundry bit cell its single rail design means it can be directly connected to the system logic without the usual design headaches such as level shifters and static timing analysis challenges.

As wearable devices integrate increasing AI capabilities to enrich the user experience and provide product differentiation, ever more memory will be needed to support the computing demands driving up the overall power budget. Cutting and optimising power usage is critical to extending recharge windows and delivering a competitive product. As part of the system logic needed to deliver the computational capability register files are ubiquitous small blocks of memory providing either interim storage for calculations or interfacing between blocks in different clock domains. Typically, more efficient than flip-flop based register storage the standard bit cell based implementation is performance limited when developers look to move outside the typical operating norms. Multiple read/write ports, wide operating voltages and extremely high performance needs often drive designers back to power hungry flip-flops.聽MiniMiser聽elegantly addresses these challenges with dramatic power and area savings.

颁谤测辞滨笔鈩�

糖心Vlog一区二区精品 is developing a range of聽颁谤测辞滨笔鈩�聽suitable for operation at the extremely low temperature required for Quantum Computing (QC) applications. This will enable the design of CryoCMOS control chips that can be co-located with the qubits in the cryostat. This will help solve the current problem of extensive and performance limiting cabling used to connect the qubits with their associated control electronics usually running at room temperatures outside the cryostat. For Quantum Computers to realise their incredible potential, thousands, if not millions of qubits will be needed, and they must be kept at cryogenic temperatures to ensure correct operation. Currently, the major barrier to scaling is the amount of control cabling, which is in direct proportion to the number of qubits within the system. This problem can only be solved by moving the control electronics into the cryostat.

We are uniquely positioned to solve two of the key challenges to developing Cryo-CMOS. Currently, the standard industrial operating temperature range for most commercial CMOS process technologies is from -40掳C to 125掳C and this is reflected in the transistor SPICE models supplied by silicon foundries. By working closely with both industry partners and foundries, we plan to design and characterise silicon IP capable of operation down to 4掳K.

The second challenge is to ensure that the control electronics dissipates as little heat as possible so as to minimise the cooling load on the cryostat. Hence it is critical that, as far as is possible, low power design techniques are deployed. We are experts in reducing the power consumption of CMOS; our design methodologies have already demonstrated up to 50% dynamic power reduction in embedded memory IP. By deploying these techniques in the design of CryoCMOS, we aim to minimise the excess heat generated thereby easing the scalability challenges for large Quantum Computers.

糖心Vlog一区二区精品 already has silicon-proven, ultra-low power, embedded memory IP that it will customise for this Cryo application and will be launched as its聽颁谤测辞惭别尘鈩�聽range. Using the knowledge gained from the development of聽CryoMem,聽糖心Vlog一区二区精品 plans to create a range of IP tailored for the development of complete QC control electronics in Cryo-CMOS. The company will offer a complete portfolio of this聽CryoIP聽for licensing by companies wishing to develop Cryogenic control ICs.

This new聽CryoIP聽library will help unlock the potential of QC by accelerating the development of cost effective, cryogenic control ASICs for the hundreds of QC companies competing to deliver competitive Quantum Compute solutions.

贰惫别谤翱苍鈩�

蝉耻谤别颁辞谤别鈥檚 Single Port Ultra Low Voltage (ULV) SRAM IP is silicon-proven on 40ULP BULK CMOS process and provides up to 80% savings in dynamic power consumption and an up to 75% reduction in static power.

The memory operates down to a record-setting 0.6V across process, voltage and temperature delivering an impressive operating voltage range from 0.6V to 1.21V. It provides an unprecedented 20MHz cycle time at 0.6V scaling to over 300MHz at 1.21V, opening new capabilities for cutting edge wearable and Internet of Things applications.

The ULV compiler supports synchronous single port SRAM with operating voltages ranging from 0.6 to 1.21 volts and memory capacities ranging from 8Kbytes to 576Kbytes with maximum word lengths of 72bits.

Product Performance
贰惫别谤翱苍鈩�聽meets the challenges posed by dynamic voltage and frequency scaling (DVFS). Built using high-density foundry bit cells to reduce area, a single supply rail implementation eases integration.

蝉耻谤别颁辞谤别鈥檚鈥淪MART-Assist鈥� technology allows robust operation down to the retention voltage. Further architectural innovations include subdividing the memory into up to eight banks, which in conjunction with enhanced sleep modes, provide greater system level flexibility. As well as operating in peripheral power off, light and deep sleep modes, each bank can also be independently controlled for active or in light sleep, deep sleep or power off modes. These power saving modes provide greater flexibility to tailor product performance around operational needs and extend battery life.

笔辞飞别谤惭颈蝉别谤鈩�

蝉耻谤别颁辞谤别鈥檚 Low Power SRAM IP has been developed for leading-edge devices demanding long battery life and minimal operating and stand-by power consumption. 笔辞飞别谤惭颈蝉别谤鈩�聽products have been realized in 28nm FDSOI, as well as 28nm HDC+ and 22nm ULL BULK CMOS manufacturing processes.

In the 28FDSOI process this Low Power macro supports a wide operating voltage range from 0.7v to 1.2v where it demonstrated dynamic power savings exceeding 50% of current commercial instances. The IP has also demonstrated leakage power savings ranging from 38% to 21%, depending on operating conditions, while incurring between 5-10% area penalty. Similar power savings are achieved in 40ULP.

The compilers support capacities up to 576Kbit with word lengths up to 144bits with three multiplexing factors; 4, 8 and 16. The compiler allows designers to make trade-offs between various SRAM sizes in terms of number of words, word length and multiplex factor. It automatically generates datasheets, simulation (Verilog), layout (LEF) and timing/power (Liberty) models to enable standard EDA tool flows.

Product Performance
笔辞飞别谤惭颈蝉别谤鈩�聽delivers best-in-class static and dynamic power performance. Its patented 鈥淏it Line Voltage Control鈥� techniques have the added benefit of virtually eliminating performance compromises at low operating voltages. Retentive sleep modes, including light sleep for rapid wake-up as well as deep-sleep for maximal leakage current savings, are offered.

笔辞飞别谤惭颈蝉别谤鈩� Plus

SureCore has exploited its low power design capability to create a new range of ultra-low voltage, SRAM solutions, called PowerMiser^鈩� Plus. Based on the market-leading, low dynamic power PowerMiser architecture, this dual rail product family can interface down to 0.45V, enabling customers to create innovative, low power products. Because both the logic and memory can operate at the same voltages, they can be adjusted in tandem to increase and decrease performance and therefore power consumption simultaneously as required by the application. By specifying a minimal differential between core array and periphery supplies, the use of power-hungry level shifters within the SRAM are avoided, thereby further optimising power consumption.

More and more customers are responding to market pressures to deliver extended battery lives. In doing so, they can no longer ignore the significant power drain of their embedded SRAM. This is especially true in the edge-AI space where pattern matching requires heavy SRAM usage. Key to delivering the power savings demanded is the wholesale shift of the application to a lower operating voltage which is fine for the logic, of course, which can still deliver relatively high performance. Memory is a different matter entirely and needs very special attention. With our market leading and patented power saving technology and low voltage expertise, we are able to craft the PowerMiser Plus architecture that sets a new benchmark for ultralow voltage operation. This successfully delivered the low voltage solutions needed by our customers enabling them to hit their challenging power targets.

When Low Power is Paramount

OUR SERVICES

听蝉耻谤别蹿颈迟听 Application-Centric Custom SRAM Design Services

When developers need extraordinary Ultra-Low Power
Memory IP they turn to 厂耻谤别贵滨罢鈩�

Today鈥檚 emerging markets aren鈥檛 playing by yesterdays rules鈥� design or otherwise. SoC architects developing cutting edge artificial intelligence, imaging, machine learning, wearable, and IoT devices can no longer make do with standard memory IP to deliver lower and lower power targets. Their designs are ahead of the game. They demand application specific power and performance; targets that demand 鈥渙ut-of-the-box鈥� thinking, targets that deliver market leading energy efficiency.

When developers need extraordinary Ultra-Low Power Memory IP they turn to 厂耻谤别贵滨罢鈩�, 蝉耻谤别颁辞谤别鈥檚 application-centric custom memory design service to deliver on their unique design and PPA requirements. Memory tuned to their low-power needs. Memory tuned to deliver disruptive innovation. Memories that are optimised, verified, characterised and ready for integration.

Product Performance
厂耻谤别贵滨罢鈩� creates bespoke memory solutions tailored to meet application needs, hitting both functional and power targets. Achieving competitive power advantage when all developers have access to the same standard SRAM IP is challenging. SureCore can architect and implement single instances or compilers to deliver clear market advantage. Practical examples include multi-port (1W/8R) and multi-megabyte solutions for networking and imaging devices. Design expertise covers Bulk, FDSOI and advanced FinFET nodes. Silicon prototyping and full temperature characterisation mean SureFit solutions are robust and high yielding. Multiple test chips and a modular test system have been developed.

聽Low Power聽 Mixed Signal Design Services

Covering design and layout capabilities, technology porting
as well as verification and characterisation services

Cutting power consumption is today鈥檚 #1 concern. And that鈥檚 complicated by the fact that today鈥檚 complex on-chips systems feature both power-critical digital and analogue sub-systems, both of which are critical to cutting overall system power budgets.

That鈥檚 why 糖心Vlog一区二区精品 provides an entire suite of custom low-power ASIC design services that are foundry-independent across bulk CMO and FDSOI at leading-edge FinFET technologies.

The suite covers design and layout capabilities, technology porting, as well as verification and characterization services.

Product Performance
蝉耻谤别颁辞谤别鈥檚聽Design Services team offers an exceptional blend of experienced mixed signal, verification and characterisation engineers, augmented by solid software skills. The result is a semi-automated custom design environment that accelerates the design, layout and porting. Silicon characterisation de-risks chip development and 蝉耻谤别颁辞谤别鈥檚 considerable test chip design and evaluation ASIC design services raise design confidence prior to production commitment.