糖心Vlog一区二区精品 Limited was established nearly a decade ago to tackle one of the semiconductor industry鈥檚 most critical challenges: Lower SoC power consumption by reducing industry-standard SRAM which can account for up to 70% of operating power. 糖心Vlog一区二区精品 assembled a world-class engineering and management team to significantly reduce both dynamic and static power across a range of devices and product applications.
糖心Vlog一区二区精品鈥檚 vision is driven by an insatiable desire to extend operating life of 鈥淎lways-on /Keep-alive鈥� circuitry from days and weeks to months and years. These new 鈥榞reen and sustainable鈥� application requirements characterizes the next generation of semiconductors, particularly SoC designs. One of the most daunting technical challenges is to support limited data processing at previously unattainably low operating voltages so that even in 鈥榓lways on鈥� mode, the majority of the SoC is powered off while awaiting an activation event.
Because of the 鈥渁lways-on /keep-alive鈥� nature of Artificial Intelligence, Machine Learning and IoT applications more and more attention is being paid to the integrated circuits (IC鈥檚) that at the core. In the emerging IoT market, the majority of SoCs are event driven; powered off until an external stimulus awakes them. Normally this requires the built-in processor and SRAM memory to undertake limited processing and operate at lowest possible voltage. However, using today鈥檚 technology, this is not possible for many applications. The processor and SRAM鈥檚 dynamic and static power consumptions are too high because the operating speed envelope is too wide and the available power-down modes lack sufficient granularity and flexibility.
糖心Vlog一区二区精品鈥檚 Smart Assist technology addresses both the flexibility of memory power control and a reduced minimum operating voltage.
糖心Vlog一区二区精品鈥檚 ultra-low power SRAM development hypothesis was to revisit the power consumption 鈥榝acts鈥� at the most basic level, challenging and questioning fundamental and well-adopted SRAM design trade-offs. This started at the SRAM architecture level and resulted in dramatically reducing dynamic power. A basic redesign of the power-down modes now manages static power consumption by banking memories to control flexibility while retaining all-important retention performance enabled a solution capable of operating from 1.21 volts down to 0.6 volts.
This white paper introduces 糖心Vlog一区二区精品鈥檚 颁辞尘辫耻搁础惭鈩� platform 鈥� SRAM architecture extensions to support In-Memory Computation. This is a useful technology for improving the power-performance of AI applications, and is particularly applicable to powerconstrained applications 鈥� for instance when AI techniques are used to improve the functionality of stand-alone devices or battery-powered but network-connected devices.
This white paper, co-written with our partners at Siemens EDA, addresses SRAM verification challenges with robust low power memory for power critical applications with Solido Variation Designer. The key elements are explored, including focused parametric tests run with Monte Carlo (MC) analysis across the PVT range and high sigma analysis, using Solido鈩� Variation Designer.
Register files have traditionally been designed for performance and area, rather than low power operation. This means using foundry-supplied bit cells, that have been optimised for a combination of read current and area. The bit cell is combined with fast acting, but often power-hungry, peripheral circuits for reads and writes in order to provide high speed access to the stored data. This results in a design that is good for high-performance applications, but inappropriate for the kinds of power-constrained applications mentioned above. For those, a register file designed for low power is required.
The proliferation of System-on-Chip (SoC) components has increased the demand for memory compilers to deliver a plethora of instances for integration into next generation products. Accurate and time efficient characterisation of the memory compiler is essential to guarantee performance across the whole instance space and process corners.
